DC-DC converters are small, lightweight, high-efficiency direct-current power sources that use semiconductor switching elements. They are widely used for electronic equipment and the like, and in recent years, the demand for small, lightweight and high-efficiency converters has increased. The basic principal of a DC-DC converter is to turn a switching element on and off at high frequency, variably control the On/OFF period ratio, that is, the duty ratio, and keep the direct-current output voltage at a constant level. Types with which a high output voltage is obtained from the input voltage with a so-called non-insulated or chopper system are called DC-DC boost converters or boosters.
A conventional, representative DC-DC boost converter (booster) is shown in FIG. 5. This booster, broadly categorizing, is constituted with two parts: booster core 100 and control 102.
Booster core 100 is comprised of an inductor 104, NMOS transistor 106, diode 108 and output capacitor 110. More specifically, inductor 104 and NMOS transistor 106 are connected in series through node N between an input terminal, to which direct-current input voltage VI is input, and a ground potential terminal, diode 108 is connected between node N and output terminal 112, and output capacitor 110 is connected between output terminal 112 and a ground potential terminal.
Control 102 is comprised of reference voltage generation circuit 114, error amplifier 116, integrator 118, clamp voltage generation circuit 120, ramp (sawtooth or triangular wave) generation circuit 122, comparators 124 and 126, logic gate circuit (AND gate) 128, and gate drive circuit 130. More specifically, reference voltage generation circuit 114 generates reference voltage VREF at a constant voltage level and supplies it to one input terminal (+) of error amplifier 116. Output voltage VO is input from booster core 100 to the other terminal (−) of error amplifier 116. Error amplifier 116 takes the difference or error between the two voltages VO and VREF, and outputs an output voltage according to the error as error signal Ve. Error signal VE is time-integrated by integrator 118, and is supplied to one input terminal (+) of comparator 124 as integrated error signal VES.
Ramp voltage, for example, sawtooth wave VRAMP, synchronized with clock CLK is supplied from ramp-generation circuit 122 to the other terminal (−) of comparator 124. Comparator 124 compares the voltage levels of the two input signals VRAMP and VES, and outputs a binary signal or pulse at H level when VRAMP<VES, and at L level when Vramp>Ves, as pulse width control signal or PWM control signal VPWM. The PWM control signal VPWM is sent to one of the input terminals of AND circuit 128.
Sawtooth wave VRAMP output from ramp-generation circuit 122 is also supplied to one input terminal (−) of the other comparator 126. Clamp voltage VCLAMP with a constant voltage level is input from clamp voltage generation circuit 120 to the other input terminal (+) of comparator 126. Comparator 126 compares the voltage levels of the two input signals VRAMP and VCLAMP, and outputs a binary signal or pulse at H level when VRAMP<VCLAMP, and one at L level when VRAMP>VCLAMP, as ON period upper limit signal VLIMIT. ON period upper limit signal VLIMIT is supplied to the other input terminal of AND circuit 128.
AND circuit 128 outputs, as switching drive signal VDRIVE, a binary signal or pulse which is at H level when both input signals VPWM and VLIMIT are at H level, and is at L level when one or both are at L level. Here, because both input signals VPWM and VLIMIT are synchronized with clock CLK, switching drive signal VDRIVE is also synchronized with clock CLK. Gate drive circuit 130 outputs gate voltage VG in response to switching drive signal VDRIVE from AND circuit 128, and NMOS transistor 106 of core part 100 is switched.
In booster core 100, the ON period is when gate voltage VG is at H level. During this period, NMOS transistor 106 is on, and inductance current IL flows to the ground potential terminal through inductor 104 and NMOS transistor 106 from the voltage input terminal, and is stored in inductor 104. The ON period is when gate voltage VG is at L level. During this period, NMOS transistor 106 is off, and electromagnetic energy stored in inductor 104 prior to that is discharged toward output capacitor 110. That is, inductance current IL from inductor 104 flows into output capacitor 110 through node N and diode 108, and output capacitor 110 is charged.
The basic operation of the booster is shown in FIG. 6. As illustrated, gate voltage VG, inductance current IL and the potential VL of node N are all synchronized with clock CLK that has constant cycle TS.
That is, gate voltage VG rises to H level from the prior L level at the start of each cycle of clock CLK, and NMOS transistor 106 comes on. During the period when gate voltage VG maintains the H level and NMOS transistor is on (ON period), inductance current IL increases with slope VI/L (L is the inductance of inductor 104). At this time, potential VL of node N is at ground potential (zero volts).
Then, during the relevant cycle, when gate voltage VG changes from H level to L level, NMOS transistor 106 goes off, switching from the ON period to the OFF period. Then when node N is disconnected from the ground potential, and assuming that the voltage drop from diode 108 is ideally zero, potential VL of node N rises to a level equal to output voltage VO, and the destination of inductance current IL is switched to output capacitor 110 from the prior ground potential terminal destination. Here, inductance current IL decreases at a slope of (VO−VI)/L.
Then, when inductance current IL has decreased to zero amperes and there is no flow, at that instant, potential VL of node N changes to a level equal to input voltage VI (potential of the voltage input terminal) from a level approximately equal to output voltage VO prior to that, and this non-current state is maintained until the end of the OFF period or cycle concerned.
When the next cycle of clock CLK begins, gate voltage VG again rises to H level from the L level prior to that, and the operation described above is repeated. However, because feedback-type PWM control is performed in control 102, the ratio of the ON period and the OFF periods, that is, the duty ratio, is changed for every cycle. FIG. 6 shows where inductance current IL has returned to zero amperes and is interrupted (called “discontinuous mode” hereafter).
FIG. 7 shows where inductance current IL in each cycle continues to flow, without returning to zero amperes, until the next cycle starts (called “continuous mode” hereafter). Such a continuous mode is reached when the On duty period is made longer.
It is generally considered that a transfer function of the booster core 100 in the discontinuous mode can be approximated as a primary pole system, and its operation is stable. On the other hand, a transfer function in the continuous mode not only operates as a secondary pole system, but has an RHP (right half-plane) zero point, and compensation for this is complicated and difficult. Therefore, stable operation and simplification of the circuit configuration are achieved by its configuration as a booster that will normally operate in discontinuous mode.
Here, when the duty for the period when NMOS transistor 106 is on is D1, and the duty for the period after NMOS transistor 106 switches to off from on until inductance current IL reaches zero amperes is D2, relative to cycle TS of clock CLK, duties D1 and D2 are represented with the following formulas based on input voltage VI, output voltage VO, inductor 104 inductance L and load current Io:
                                                                        D                1                            =                            ⁢                                                                                                                  (                                                                              V                            o                                                    -                                                      V                            i                                                                          )                                            ⁢                                              I                        o                                                                                    V                      i                      2                                                        ⁢                                                            2                      ⁢                      L                                                              T                      S                                                                                                                                                              =                                ⁢                                                                                                    2                        ⁢                        L                                                                                              R                          o                                                ⁢                                                  T                          S                                                                                      ⁡                                          [                                                                                                    (                                                                                          V                                o                                                                                            V                                i                                                                                      )                                                    2                                                -                                                                              V                            o                                                                                V                            i                                                                                              ]                                                                                  ,                                                where                  ⁢                                                                          ⁢                                      R                    O                                                  =                                                      V                    O                                    /                                      I                    O                                                                                                          (        1        )                                          D          2                =                                            V              i                                                      V                o                            -                              V                i                                              ⁢                      D            1                                              (        2        )            Pertaining to ON duty D1, the condition to maintain a discontinuous mode is that D1 be smaller than ON duty D in a continuous mode, so it is stipulated by following equation (3).
                                          D            1                    <          D                =                  1          -                                    V              i                                      V              o                                                          (        3        )            
In the booster in FIG. 5, the ON period within each cycle is primarily influenced by PWM control signal VPWM output from comparator 124, and is ultimately determined by the logical product (AND condition) of PWM control signal VPWM and ON period upper limit signal VLIMIT output from comparator 126. That is, the pulse width of PWM control signal VPWM is subject to the restriction on the pulse width of ON period upper limit signal VLIMIT, that is, the ON period upper limit, through AND circuit 128, so that the pulse width (ON period) of switching drive signal Vdrive will not exceed the ON period upper limit.
Therefore, from equation (3) above, by setting the ON period upper limit stipulated by ON period upper limit signal VLIMIT to {1−(VI/VO)}·VS (where VS is the peak value of sawtooth wave VRAMP), discontinuous mode operation can be realized wherein shifting to a continuous mode is restricted. In this case, duty DC of ON period upper limit signal VLIMIT is represented with equation (4) below.
                              D          C                =                              V            CLAMP                                V            S                                              (        4        )            
An example of operation when load current IO varies in the increasing direction above a steady value over a certain period TA in the booster in FIG. 5 is shown in FIG. 8 with the waveforms of various parts.
As shown in FIG. 8, when load current IO varies in the increasing direction, output voltage VO becomes lower than reference voltage VREF, the voltage level of error signal VES rises because of this, the pulse width (H level period) of PWM control signal VPWM becomes larger, and the period for which NMOS transistor 106 is on (ON period) becomes longer. When the ON period becomes longer, inductance current IL increases, more energy is supplied to output capacitor 110 from inductor 104, and output voltage VO rises toward reference voltage VREF.
Then when output voltage VO rises and exceeds reference voltage VREF, the length of time during which NMOS transistor 106 is on (ON period) becomes shorter, the energy supplied to output capacitor 110 from inductor 104 decreases, and output voltage VO drops toward reference voltage VREF.
In this feedback-type PWM control, when the pulse width of PWM control signal VPWM exceeds pulse width TS·DC of ON period upper limit signal VLIMIT, it is subject to the upper limit restriction, and the pulse width of ON period upper limit signal VLIMIT, and then the ON period (ON period) of NMOS transistor 106 becomes TS·DC in order not to exceed it, that is, in order not to shift to continuous mode operation from discontinuous mode operation.
In a conventional booster as described above, if each of the elements that constitute booster core 100 has the ideal characteristics, the conditions in equations (3) and (4) above are effective in restricting a shift to a continuous mode and for realizing normal discontinuous mode operation. In actuality, however, duty DC for the required ON period changes due to parasitic components in inductor 104, NMOS transistor 106, diode 108 and output capacitor 110, so the conditions above are not sufficient.
Also, in applications where input voltage VI or output voltage VO is variable, when the effects of ambient temperature or process fluctuation are taken into account, setting duty DC for the ON period upper limit uniquely, as with the conventional duty control method described above, is not appropriate. For example, while it is possible to set DC to a smaller value beforehand, there is the risk that excessive restriction will diminish the load characteristics of output voltage VO or the responsiveness to sudden load changes. On the other hand, when DC is set to a larger value, the possibility of the operating mode shifting from discontinuous mode operation to continuous mode operation becomes greater, and there is the risk that the stability of booster operation will be diminished.
An example of shifting to continuous operating mode from discontinuous operating mode with an abrupt load change and the output voltage becoming unstable in the booster in FIG. 5 is shown with simulated waveforms in FIG. 9.
In FIG. 9, when load current Io is changed from 1 mA (milliamperes) to 29 mA at T=5 ms, output voltage Vo starts to drop, but output (error signal) Ves of error amplifier 116 begins to rise. Along with this, the pulse width of PWM control signal Vpwm becomes larger, and inductance current IL also gradually increases.
From T=5 ms to 5.05 ms, inductance current IL returns to zero (where IL=0 A) at each cycle or switching cycle and operation is in discontinuous mode. After T=5.05 ms, however, rather than returning to IL=0 A in each cycle, there is a shift to continuous mode. With the shift to continuous mode, booster operation becomes unstable, and low-frequency fluctuation (ringing) appears in output voltage Vo.
In recent years, applications using source voltage boosted from a single lithium battery, such as light-emitting diodes (LED) mounted in portable electronic equipment, or liquid crystal displays (LCD), have increased. With such applications, many of the boosters that are used operate in discontinuous mode where load current is not that large, from several mA to around 20 mA. For the output voltage of this type of booster, stability with little AC fluctuation, rather than DC or absolute value accuracy, is generally considered important.
The present invention was devised taking into consideration the problems in the prior art as described above, with the objective of providing a DC-DC boost converter (booster) that is not subject to the effects of the usage environment or variation in circuit elements, and with which discontinuous mode operation can be maintained efficiently without generally diminishing load characteristics or responsiveness.